規格 | 64Kx36 |
---|---|
VccQ | 2.5V |
電壓 | 2.5V |
tKQ | 2.6, 3.1 |
速度(MHz) | 250 |
腳位/封裝 | QFP(100) |
狀態 | Prod |
評注 | P |
產品系列 | 61 = 高速 |
焊接 | [空白] = SnPb |
温規 | I = 工業級 (-40C to +85°C) |
IS61NVP6436A-250TQI 特徵
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle
- Individual Byte Write Control
- Single R/W (Read/Write) control pin
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control us- ing MODE input
- Three chip enables for simple depth expansion and address pipelining
- Power Down mode
- Common data inputs and data outputs
- CKE pin to enable clock and suspend operation
- JEDEC 100-pin TQFP package
- Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
- Industrial temperature available
概觀
, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,