規格 256Kx72
VccQ 2.5/3.3V
電壓 3.3V
tKQ 6.5, 7.5
速度(MHz) 133, 117
腳位/封裝 BGA(209)
狀態 Prod
型號別 IBIS, BSDL
評注 F

IS61NLF25672-6 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages
  • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,