1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. No-Wait(ZBT)
  5. 3.3V
  6. 18M 256Kx72
  7. BGA(209)
  8. IS61NLF25672-6

  IS61NLF25672-6

Datasheet
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Density 18M
Org 256Kx72
Vcc 3.3V
VccQ 2.5/3.3V
Status Prod
tKQ(ns) 6.5, 7.5
Pkg Pins BGA(209)
Speed Mhz 133, 117
Comment Prev Rev F
Datasheet
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IS61NLF25672-6 Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single Read/Write control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages
  • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single Read/Write control pin , Clock controlled, registered address,

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS61NLF25672-6-TR IS61NLF25672-7
IS61NLF25672 IS61NLF25672-7-TR