IS45S32800J

容量	256M
規格	8Mx32
電壓	3.3V
類型	SDR
刷新	4K
速度	166, 143, 133
狀態	Prod
評注
腳位數	TSOP(54), BGA(90)
產品系列	45 = SDR Automotive grade
字數	800 = 8M
工作電壓範圍	S = 3.3V SDR
總線寬度	32 = x32

數據表

索取報價

IS45S32800J 特徵

Clock frequency:166, 143, 133 MHz
Fully synchronous; all signals referenced to a positive clock edge
Internal bank for hiding row access/precharge
Single Power supply: 3.3V + 0.3V
LVTTL interface
Programmable burst length
- (1, 2, 4, 8, full page)
Programmable burst sequence: Sequential/Interleave
Auto Refresh (CBR)
Self Refresh
4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command OPTIONS
Package: 90-ball TF-BGA, 86-pin TSOP2

概觀

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized in 2Meg x 32 bit x 4 Banks.

IC 編號	可用數量	IC 編號	可用數量
IS45S32800J-6BLA1	6,190	IS45S32800J-7BLA2	44
IS45S32800J-6BLA1-TR	6,745	IS45S32800J-7BLA2-TR
IS45S32800J-6TLA1	2,160	IS45S32800J-7TLA1	6,126
IS45S32800J-6TLA1-TR	6,521	IS45S32800J-7TLA1-TR	6,500
IS45S32800J-7BLA1	6,800	IS45S32800J-7TLA2
IS45S32800J-7BLA1-TR	7,500	IS45S32800J-7TLA2-TR

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

6,190

6,745