IS45S32800J

Density	256M
Org	8Mx32
Vcc	3.3V
Type	SDR
Refresh	4K
Speed	166, 143, 133
Status	Prod
Comment
Pkg Pins	TSOP(54), BGA(90)
Product Family	45 = SDR Automotive grade
Number Of Words	800 = 8M
Operating Voltage Range	S = 3.3V SDR
Bus Width	32 = x32

Datasheet

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IS45S32800J Features

Clock frequency:166, 143, 133 MHz
Fully synchronous; all signals referenced to a positive clock edge
Internal bank for hiding row access/precharge
Single Power supply: 3.3V + 0.3V
LVTTL interface
Programmable burst length
- (1, 2, 4, 8, full page)
Programmable burst sequence: Sequential/Interleave
Auto Refresh (CBR)
Self Refresh
4096 refresh cycles every 16ms (A2 grade) or 64 ms (Commercial, Industrial, A1 grade)
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command OPTIONS
Package: 90-ball TF-BGA, 86-pin TSOP2

Overview

ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized in 2Meg x 32 bit x 4 Banks.

Related Part Number(s)

Description	Available Qty	Description	Available Qty
IS45S32800J-6BLA1	6,190	IS45S32800J-7BLA2	44
IS45S32800J-6BLA1-TR	6,745	IS45S32800J-7BLA2-TR
IS45S32800J-6TLA1	2,160	IS45S32800J-7TLA1	6,126
IS45S32800J-6TLA1-TR	6,521	IS45S32800J-7TLA1-TR	6,500
IS45S32800J-7BLA1	6,800	IS45S32800J-7TLA2
IS45S32800J-7BLA1-TR	7,500	IS45S32800J-7TLA2-TR