IS45S16402J-7TLA2

容量	64M
規格	4Mx16
電壓	3.3V
類型	SDR
刷新	4K
速度	7 = 143MHz
狀態	Prod
評注	Reduced Strength Output Drive
腳位數	TSOP2(54), BGA(54), BGA(60)
產品系列	45 = SDR Automotive grade
温度等级	A2 = Automotive Grade (-40°C to +105°C)
焊料類型	L = 100% matte Sn
字數	402 = 4M
Generation	J = J
工作電壓範圍	S = 3.3V SDR
總線寬度	16 = x16
腳位/封裝	T = TSOP

數據表

索取報價

IS45S16402J-7TLA2 特徵

Clock frequency: 200, 166, 143, 133 MHz
Fully synchronous; all signals referenced to a positive clock edge
Internal bank for hiding row access/precharge
Single 3.3V power supply
LVTTL interface
Reduced strength output drive: 12-15mA
Programmable burst length
- (1, 2, 4, 8, full page)
Programmable burst sequence: Sequential/Interleave
Self refresh modes
Auto refresh (CBR)
4096 refresh cycles every 64 ms (Com, Ind, A1 grade) or 16ms (A2 grade)
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command OPTIONS
Package: 54-pin TSOP II 54-ball TF-BGA (8mm x 8mm) 60-ball TF-BGA (10.1mm x 6.4mm)

概觀

ISSI's 64Mb Synchronous DRAM is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量