IS45S16400E

容量	64M
規格	4Mx16
電壓	3.3V
類型	SDR
刷新	4K
速度	166, 143
狀態	Contact ISSI
評注
腳位數	TSOP2(54)
產品系列	45 = SDR Automotive grade
字數	400 = 4M
工作電壓範圍	S = 3.3V SDR
總線寬度	16 = x16

數據表

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IS45S16400E 特徵

Clock frequency: 166, 143 MHz
Fully synchronous; all signals referenced to a positive clock edge
Internal bank for hiding row access/precharge
Single 3.3V power supply
LVTTL interface
Programmable burst length
- (1, 2, 4, 8, full page)
Programmable burst sequence: Sequential/Interleave
Self refresh modes
4096 refresh cycles every 16ms (A2 grade) or 64ms (A1 grade)
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write operations capability
Burst termination by burst stop and precharge command
Byte controlled by LDQM and UDQM
Package: 400-mil 54-pin TSOP II
Lead-free package is available

概觀

ISSI's 64Mb Synchronous DRAM IS45S16400E is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

IC 編號	庫存數量	可用數量	IC 編號	可用數量
IS45S16400E-6TLA1		108	IS45S16400E-7TLA1-TR	1,500
IS45S16400E-6TLA1-TR		1,500	IS45S16400E-7TLA2	215
IS45S16400E-7TLA1	30,800	77	IS45S16400E-7TLA2-TR	1,500

IS45S16400E 特徵

概觀

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