IS49NLC96400A-25WBL-TR

容量 576M
規格 64Mx9
狀態 Prod
評注
接口 Common I/O
腳位數 BGA(144)
配置 96400 = 64M x 9
Generation A = A
ROHS版 L = Lead-free (RoHS compliant)
Package Number WB = 144 - ball WBGA (RLDRAM 2)
I / O類型 C = Common I/O
溫度範圍 = Commercial (0C to 70°C)
產品系列 49NL = RLDRAM 2
包裝代碼 WB = WB
速度等級 25 = tCK = 2.5ns; tRC = 20ns
外包裝 Tape on Reel

IS49NLC96400A-25WBL-TR 特徵

  • 533MHz DDR operation (1.067 Gb/s/pin data rate) 38.4Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
  • Differential input clocks (CK, CK#)
  • Differential input data clocks (DKx, DKx#)
  • On-die DLL generates CK edge-aligned data and
  • Reduced cycle time (15ns at 533MHz)
  • 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) 8 internal banks
  • Non-multiplexed addresses (address multiplexing option available)
  • SRAM-type interface
  • Programmable READ latency (RL), row cycle time, and burst sequence length
  • Balanced READ and WRITE latencies in order to optimize data bus utilization
  • Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. OPTIONS
  • Package:  144-ball WBGA (lead-free) output data clock signals
  • Data valid signal (QVLD)
  • HSTL I/O (1.5V or 1.8V nominal)
  • On-die termination (ODT) RTT
  • Operating temperature: 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C ) Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C)
  • Configuration:  64Mx9  32Mx18  16Mx36
 

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