規格 32Mx18
接口 Common I/O
速度 25 = tCK = 2.5ns; tRC = 20ns
腳位/封裝 BGA(144)
狀態 Prod
產品系列 49NL = RLDRAM®2
焊接 L = 無鉛
温規 I = 工業級 (-40C to +85°C)
外包裝 卷轴包

IS49NLC18320-25WBLI-TR 特徵

  • 400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency) Reduced cycle time (15ns at 400MHz) 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) 8 internal banks
  • Non-multiplexed addresses (address multiplexing option
  • available) SRAM-type interface Programmable READ latency (RL), row cycle time, and burst sequence length Balanced READ and WRITE latencies in order to optimize data bus utilization Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. OPTIONS Differential input clocks (CK, CK#) Differential input data clocks (DKx, DKx#)
  • On-die DLL generates CK edge-aligned data and output data clock signals Data valid signal (QVLD) HSTL I/O (1.5V or 1.8V nominal) 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
  • On-die termination (ODT) RTT
  • Operating temperature: IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C)


Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.