IS49NLC18320-25EWBL-TR

容量	576M
規格	32Mx18
狀態	Prod
評注
接口	Common I/O
腳位數	BGA(144)
產品系列	49NL = RLDRAM 2
配置	18320 = 32M x 18
包裝代碼	WB = WB
速度等級	25E = tCK = 2.5ns; tRC = 15ns
ROHS版	L = Lead-free (RoHS compliant)
Package Number	WB = 144 - ball WBGA (RLDRAM 2)
I / O類型	C = Common I/O
溫度範圍	= Commercial (0C to 70°C)
外包裝	Tape on Reel

數據表

索取報價

IS49NLC18320-25EWBL-TR 特徵

400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency) Reduced cycle time (15ns at 400MHz) 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) 8 internal banks
Non-multiplexed addresses (address multiplexing option
available) SRAM-type interface Programmable READ latency (RL), row cycle time, and burst sequence length Balanced READ and WRITE latencies in order to optimize data bus utilization Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. OPTIONS Differential input clocks (CK, CK#) Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and output data clock signals Data valid signal (QVLD) HSTL I/O (1.5V or 1.8V nominal) 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
Operating temperature: IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C)

概觀

Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS49NLC18320-25EWBL

IS49NLC18320-25WBLI-TR

IS49NLC18320-25B

6,725

IS49NLC18320-33B

6,558