| 容量 | 18M |
|---|---|
| 規格 | 1Mx18 |
| 陣 | 2 |
| 狀態 | Prod |
| 速度Mhz | 250, 300, 333 |
| 評論上一版本 | 2.5 Cycle Read Latency |
| 產品系列 | 61 = QUAD/P DDR-2/P |
| 配置 | 1M18 = 1M x18 |
| 包裝代碼 | B4 = 165 ball BGA (13 x 15 mm) |
| ROHS版 | = Leaded |
| 突發類型 | B2 = Burst 2 |
| 硅片版本 | A = A |
| 讀延時（RL） | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT選項 | blank = No ODT |
| 產品類別 | QDP = QUADP |
| 溫度範圍 | blank = Commercial (0°C to 70°C) |
| 速度 | 333 = 333MHz |
| 外包裝 | Tape on Reel |
The 18MB IS61QDPB251236A/A1/A2 and IS61QDPB21M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operation of these QUADP (Burst of 2) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Read and write performed in double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the K clock. The K and K# clocks are used to time the data-outs. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interface.