規格 1Mx18
2
速度(MHz) 250
腳位/封裝 M3 = 165-ball BGA (15 x 17 mm)
狀態 Prod
型號別 ibis/verilog
評注 2.5 Cycle Read Latency
產品系列 61 = 高速
產品類別 QDP = QUADP
讀延時(RL) [空白] = 2.5 clock cycles
ODT選項 A2 = 選項2
焊接 L = 無鉛
温規 I = 工業級 (-40C to +85°C)
外包裝 卷轴包
相關IC编號
IS61QDPB21M18A2-250M3LI
IS61QDPB21M18A-250B4
IS61QDPB21M18A-250B4-TR
IS61QDPB21M18A-250B4I
IS61QDPB21M18A-250B4I-TR
IS61QDPB21M18A-250B4L
IS61QDPB21M18A-250B4L-TR
IS61QDPB21M18A-250B4LI
IS61QDPB21M18A-250B4LI-TR
IS61QDPB21M18A-250M3
IS61QDPB21M18A-250M3-TR
IS61QDPB21M18A-250M3I
IS61QDPB21M18A-250M3I-TR
IS61QDPB21M18A-250M3L
IS61QDPB21M18A-250M3L-TR
IS61QDPB21M18A-250M3LI
IS61QDPB21M18A-250M3LI-TR
IS61QDPB21M18A-300B4
IS61QDPB21M18A-300B4-TR
IS61QDPB21M18A-300B4I
IS61QDPB21M18A-300B4I-TR
IS61QDPB21M18A-300B4L
IS61QDPB21M18A-300B4L-TR
IS61QDPB21M18A-300B4LI
IS61QDPB21M18A-300B4LI-TR
IS61QDPB21M18A-300M3
IS61QDPB21M18A-300M3-TR
IS61QDPB21M18A-300M3I
IS61QDPB21M18A-300M3I-TR
IS61QDPB21M18A-300M3L
IS61QDPB21M18A-300M3L-TR
IS61QDPB21M18A-300M3LI
IS61QDPB21M18A-300M3LI-TR
IS61QDPB21M18A-333B4
IS61QDPB21M18A-333B4-TR
IS61QDPB21M18A-333B4I
IS61QDPB21M18A-333B4I-TR
IS61QDPB21M18A-333B4L
IS61QDPB21M18A-333B4L-TR
IS61QDPB21M18A-333B4LI
IS61QDPB21M18A-333B4LI-TR
IS61QDPB21M18A-333M3
IS61QDPB21M18A-333M3-TR
IS61QDPB21M18A-333M3I
IS61QDPB21M18A-333M3I-TR
IS61QDPB21M18A-333M3L
IS61QDPB21M18A-333M3L-TR
IS61QDPB21M18A-333M3LI
IS61QDPB21M18A-333M3LI-TR
IS61QDPB21M18A1-250B4
IS61QDPB21M18A1-250B4-TR
IS61QDPB21M18A1-250B4I
IS61QDPB21M18A1-250B4I-TR
IS61QDPB21M18A1-250B4L
IS61QDPB21M18A1-250B4L-TR
IS61QDPB21M18A1-250B4LI
IS61QDPB21M18A1-250B4LI-TR
IS61QDPB21M18A1-250M3
IS61QDPB21M18A1-250M3-TR
IS61QDPB21M18A1-250M3I
IS61QDPB21M18A1-250M3I-TR
IS61QDPB21M18A1-250M3L
IS61QDPB21M18A1-250M3L-TR
IS61QDPB21M18A1-250M3LI
IS61QDPB21M18A1-250M3LI-TR
IS61QDPB21M18A1-300B4
IS61QDPB21M18A1-300B4-TR
IS61QDPB21M18A1-300B4I
IS61QDPB21M18A1-300B4I-TR
IS61QDPB21M18A1-300B4L
IS61QDPB21M18A1-300B4L-TR
IS61QDPB21M18A1-300B4LI
IS61QDPB21M18A1-300B4LI-TR
IS61QDPB21M18A1-300M3
IS61QDPB21M18A1-300M3-TR
IS61QDPB21M18A1-300M3I
IS61QDPB21M18A1-300M3I-TR
IS61QDPB21M18A1-300M3L
IS61QDPB21M18A1-300M3L-TR
IS61QDPB21M18A1-300M3LI
IS61QDPB21M18A1-300M3LI-TR
IS61QDPB21M18A1-333B4
IS61QDPB21M18A1-333B4-TR
IS61QDPB21M18A1-333B4I
IS61QDPB21M18A1-333B4I-TR
IS61QDPB21M18A1-333B4L
IS61QDPB21M18A1-333B4L-TR
IS61QDPB21M18A1-333B4LI
IS61QDPB21M18A1-333B4LI-TR
IS61QDPB21M18A1-333M3
IS61QDPB21M18A1-333M3-TR
IS61QDPB21M18A1-333M3I
IS61QDPB21M18A1-333M3I-TR
IS61QDPB21M18A1-333M3L
IS61QDPB21M18A1-333M3L-TR
IS61QDPB21M18A1-333M3LI
IS61QDPB21M18A1-333M3LI-TR
IS61QDPB21M18A2-250B4
IS61QDPB21M18A2-250B4-TR
IS61QDPB21M18A2-250B4I
IS61QDPB21M18A2-250B4I-TR
IS61QDPB21M18A2-250B4L
IS61QDPB21M18A2-250B4L-TR
IS61QDPB21M18A2-250B4LI
IS61QDPB21M18A2-250B4LI-TR
IS61QDPB21M18A2-250M3
IS61QDPB21M18A2-250M3-TR
IS61QDPB21M18A2-250M3I
IS61QDPB21M18A2-250M3I-TR
IS61QDPB21M18A2-250M3L
IS61QDPB21M18A2-250M3L-TR
IS61QDPB21M18A2-300B4
IS61QDPB21M18A2-300B4-TR
IS61QDPB21M18A2-300B4I
IS61QDPB21M18A2-300B4I-TR
IS61QDPB21M18A2-300B4L
IS61QDPB21M18A2-300B4L-TR
IS61QDPB21M18A2-300B4LI
IS61QDPB21M18A2-300B4LI-TR
IS61QDPB21M18A2-300M3
IS61QDPB21M18A2-300M3-TR
IS61QDPB21M18A2-300M3I
IS61QDPB21M18A2-300M3I-TR
IS61QDPB21M18A2-300M3L
IS61QDPB21M18A2-300M3L-TR
IS61QDPB21M18A2-300M3LI
IS61QDPB21M18A2-300M3LI-TR
IS61QDPB21M18A2-333B4
IS61QDPB21M18A2-333B4-TR
IS61QDPB21M18A2-333B4I
IS61QDPB21M18A2-333B4I-TR
IS61QDPB21M18A2-333B4L
IS61QDPB21M18A2-333B4L-TR
IS61QDPB21M18A2-333B4LI
IS61QDPB21M18A2-333B4LI-TR
IS61QDPB21M18A2-333M3
IS61QDPB21M18A2-333M3-TR
IS61QDPB21M18A2-333M3I
IS61QDPB21M18A2-333M3I-TR
IS61QDPB21M18A2-333M3L
IS61QDPB21M18A2-333M3L-TR
IS61QDPB21M18A2-333M3LI
IS61QDPB21M18A2-333M3LI-TR


IS61QDPB21M18A2-250M3LI-TR 特徵

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.5 Cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data valid pin (QVLD).
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte Write capability.
  • Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • optionally on data input, K/K#, and BWx#. The end of top mark (A/A1/A2) is to define options. IS61QDPB251236A : Don’t care ODT function and pin connection IS61QDPB251236A1 : Option1 IS61QDPB251236A2 : Option2 Refer to more detail description at page 6 for each ODT option. OCTOBER 2014 and are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the for a description of the basic operations of these SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Read and write performed in double data rate. The following are registered internally on the rising edge of the K clock:
  • Read address
  • Read enable
  • Write enable
  • Data-in for early writes The following are registered on the rising edge of the K# clock:
  • Write address
  • Byte writes