規格 512Kx36
2
速度(MHz) 300
腳位/封裝 M3 = 165-ball BGA (15 x 17 mm)
狀態 Prod
型號別 ibis/verilog
產品系列 61 = 高速
產品類別 QD = QUAD
讀延時(RL) [空白] = 2.5 clock cycles
焊接 L = 無鉛
温規 [空白] = 商規 (0C to +70°C)
相關IC编號
IS61QDB251236C-300M3L-TR
IS61QDB251236C-250B4
IS61QDB251236C-250B4-TR
IS61QDB251236C-250B4I
IS61QDB251236C-250B4I-TR
IS61QDB251236C-250B4L
IS61QDB251236C-250B4L-TR
IS61QDB251236C-250B4LI
IS61QDB251236C-250B4LI-TR
IS61QDB251236C-250M3
IS61QDB251236C-250M3-TR
IS61QDB251236C-250M3I
IS61QDB251236C-250M3I-TR
IS61QDB251236C-250M3L
IS61QDB251236C-250M3L-TR
IS61QDB251236C-250M3LI
IS61QDB251236C-250M3LI-TR
IS61QDB251236C-300B4
IS61QDB251236C-300B4-TR
IS61QDB251236C-300B4I
IS61QDB251236C-300B4I-TR
IS61QDB251236C-300B4L
IS61QDB251236C-300B4L-TR
IS61QDB251236C-300B4LI
IS61QDB251236C-300B4LI-TR
IS61QDB251236C-300M3
IS61QDB251236C-300M3-TR
IS61QDB251236C-300M3I
IS61QDB251236C-300M3I-TR
IS61QDB251236C-300M3LI
IS61QDB251236C-300M3LI-TR
IS61QDB251236C-333B4
IS61QDB251236C-333B4-TR
IS61QDB251236C-333B4I
IS61QDB251236C-333B4I-TR
IS61QDB251236C-333B4L
IS61QDB251236C-333B4L-TR
IS61QDB251236C-333B4LI
IS61QDB251236C-333B4LI-TR
IS61QDB251236C-333M3
IS61QDB251236C-333M3-TR
IS61QDB251236C-333M3I
IS61QDB251236C-333M3I-TR
IS61QDB251236C-333M3L
IS61QDB251236C-333M3L-TR
IS61QDB251236C-333M3LI
IS61QDB251236C-333M3LI-TR
IS61QDB251236C-400B4
IS61QDB251236C-400B4-TR
IS61QDB251236C-400B4I
IS61QDB251236C-400B4I-TR
IS61QDB251236C-400B4L
IS61QDB251236C-400B4L-TR
IS61QDB251236C-400B4LI
IS61QDB251236C-400B4LI-TR
IS61QDB251236C-400M3
IS61QDB251236C-400M3-TR
IS61QDB251236C-400M3I
IS61QDB251236C-400M3I-TR
IS61QDB251236C-400M3L
IS61QDB251236C-400M3L-TR
IS61QDB251236C-400M3LI
IS61QDB251236C-400M3LI-TR


IS61QDB251236C-300M3L 特徵

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Read address
  • Read enable
  • Write enable
  • Byte writes
  • Data-in for early writes The following are registered on the rising edge of the K# clock:
  • Write address
  • Byte writes

概觀

The Mb synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the.