IS61DDB21M18A

容量	18M
規格	1Mx18
陣	2
狀態	Prod
速度Mhz	250, 300, 333
評論上一版本

容量

18M

規格

1Mx18

陣

狀態

Prod

速度Mhz

250, 300, 333

評論上一版本

IS61DDB21M18A 特徵

512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two input clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
Read/write address
Read enable
Write enable
Byte writes for first burst address
Data-in for first burst address The following are registered on the rising edge of the K# clock:
Byte writes for second burst address

概觀

The 18Mb IS61DDB251236A and IS61DDB21M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs.

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS61DDB21M18A-250B4

IS61DDB21M18A-300M3

IS61DDB21M18A-250B4-TR

IS61DDB21M18A-300M3-TR

IS61DDB21M18A-250B4I

IS61DDB21M18A-300M3I