1. 矽成
2. Mobile DRAM
3. 低電壓/移動SDR SDRAM
4. 前置低電壓移動SDRAM
5. 1.8V
6. TSOP
7. IS42VS32200E-10TL

IS42VS32200E-10TL 特徵

• Clock frequency: 133, 100 MHz
• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge
• Single 1.8V power supply
• LVTTL interface
• Programmable burst length: (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Available in 400-mil 86-pin TSOP II and 90-ball BGA

概觀

ISSI's 64Mb Synchronous DRAM IS42VS32200E is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high- speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.