容量 2G
規格 256Mx8
類型 DDR2
電壓 1.8V
刷新 8K
速度 3 = up to 333 Mhz
腳位/封裝 BGA(60)
狀態 NR
型號別 IBIS
產品系列 46 = 車規DDR/DDR2/DDR3/DDR4
總線寬度 8 = x8
字數 2560 = 256M
代/版本 B
CL(CAS延遲) D = 5
焊接 L = SnAgCu
温規 A1 = 車規 (-40C to +85°C)
相關IC编號
IS46DR82560B-3DBLA1-TR

IS46DR82560B-3DBLA1 特徵

  • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Double data rate interface: two data transfers per clock cycle
  • Differential data strobe (DQS, DQS)
  • 4-bit prefetch architecture
  • On chip DLL to align DQ and DQS transitions with CK
  • 8 internal banks for concurrent operation
  • Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported
  • Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5, and 6 supported
  • WRITE latency = READ latency - 1 tCK
  • Programmable burst lengths: 4 or 8
  • Adjustable data-output drive strength, full and reduced strength options
  • On-die termination (ODT) OPTIONS
  • Configuration(s): 256Mx8 (32Mx8x8 banks) IS43/46DR82560B 128Mx16 (16Mx16x8 banks) IS43/46DR16128B
  • Package: x8: 60-ball BGA (10.5mm x 13mm) x16: 84-ball WBGA (10.5mm x 13.5mm) Timing
    • Cycle time 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D

概觀

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.