IS46DR82560B-3DBLA1

Density	2G
Org	256Mx8
Vcc	1.8V
Type	DDR2
Refresh	8K
Speed	3 = 333MHz
Status	NR
Comment
Pkg Pins	BGA(60)
Product Family	46 = DDR/DDR2/DDR3/DDR4 Automotive grade
Temp. Grade	A1 = Automotive Grade (-40°C to +85°C)
Solder Type	L = SnAgCu
Number Of Words	2560 = 256M
CL (CAS Latency)	D = 5
Generation	B = B
Operating Voltage Range	DR = 1.8V DDR2
Bus Width	8 = x8
Package Type	B = BGA

Datasheet

Get Quote

IS46DR82560B-3DBLA1 Features

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5, and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT) OPTIONS
Configuration(s): 256Mx8 (32Mx8x8 banks) IS43/46DR82560B 128Mx16 (16Mx16x8 banks) IS43/46DR16128B
Package: x8: 60-ball BGA (10.5mm x 13mm) x16: 84-ball WBGA (10.5mm x 13.5mm) Timing
- Cycle time 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D

Overview

ISSI's 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

Related Part Number(s)

Description	Stock Qty	Available Qty
IS46DR82560B-3DBLA1-TR