IS61NLP12818A-250TQ-TR

容量	2M
規格	128Kx18
電壓	3.3V
VccQ	2.5/3.3V
狀態	Prod
tKQ(ns)	2.6, 3.1
腳位數	QFP(100)
速度Mhz	250, 200
評論上一版本	P

數據表

索取報價

IS61NLP12818A-250TQ-TR 特徵

100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address, data and control
Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP package
Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
Industrial temperature available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,

IC 編號

庫存數量

可用數量

IC 編號

庫存數量

可用數量

IS61NLP12818A-250TQ

IS61NLP12818A-200TQLI

IS61NLP12818A-200TQ

IS61NLP12818A-200TQLI-TR

IS61NLP12818A-200TQ-TR

IS61NLP12818A-250TQI