1. ISSI
  2. SRAM
  3. Synchronous SRAM
  4. No-Wait(ZBT)
  5. 3.3V
  6. 2M 128Kx18
  7. QFP(100)
  8. IS61NLP12818A-250TQ-TR

  IS61NLP12818A-250TQ-TR

Datasheet
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Density 2M
Org 128Kx18
Vcc 3.3V
VccQ 2.5/3.3V
Status Prod
tKQ(ns) 2.6, 3.1
Pkg Pins QFP(100)
Speed Mhz 250, 200
Comment Prev Rev P
Datasheet
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IS61NLP12818A-250TQ-TR Features

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP package
  • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • Industrial temperature available

Overview

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS61NLP12818A-250TQ IS61NLP12818A-200TQLI
IS61NLP12818A-200TQ IS61NLP12818A-200TQLI-TR
IS61NLP12818A-200TQ-TR IS61NLP12818A-250TQI
IS61NLP12818A-200TQI IS61NLP12818A-250TQI-TR
IS61NLP12818A-200TQI-TR