IS61QDP2B21M18C1-400B4LI-TR

容量	18M
規格	1Mx18
陣	2
狀態	Prod
速度Mhz	300, 333, 400, 450
評論上一版本	2.0 Cycle Read Latency
產品系列	61 = QUAD/P DDR-2/P
配置	1M18 = 1M x18
包裝代碼	B4 = 165 ball BGA (13 x 15 mm)
ROHS版	L = Lead-free
突發類型	B2 = Burst 2
硅片版本	C = C
讀延時（RL）	2 = 2.0 clock cycles
ODT選項	1 = ODT Option 1 If ODT = HIGH or floating, a high range termination resistance is selected. If ODT = LOW, a low range termination resistance is selected.
產品類別	QDP = QUADP
溫度範圍	I = Industrial (-40°C to +85°C)
速度	400 = 400MHz
外包裝	Tape on Reel

數據表

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IS61QDP2B21M18C1-400B4LI-TR 特徵

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports. 2.0 Cycle read latency.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
Data valid pin (QVLD).
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs. The following are registered internally on the rising edge of the K clock:
Read address
Read enable
Write enable
Data-in for early writes The following are registered on the rising edge of the K# clock:
Write address
Byte writes
Data-in for second burst addresses
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte Write capability.
Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
Programmable impedance output drivers via 5x user- supplied precision resistor.
ODT (On Die Termination) feature is supported

概觀

The are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the.

相關IC编號

IC 編號	庫存數量	可用數量	IC 編號	庫存數量	可用數量
IS61QDP2B21M18C-333B4			IS61QDP2B21M18C1-333M3
IS61QDP2B21M18C-333B4-TR			IS61QDP2B21M18C1-333M3-TR
IS61QDP2B21M18C-333B4I			IS61QDP2B21M18C1-333M3I
IS61QDP2B21M18C-333B4I-TR			IS61QDP2B21M18C1-333M3I-TR
IS61QDP2B21M18C-333B4L			IS61QDP2B21M18C1-333M3L
IS61QDP2B21M18C-333B4L-TR			IS61QDP2B21M18C1-333M3L-TR
IS61QDP2B21M18C-333B4LI			IS61QDP2B21M18C1-333M3LI
IS61QDP2B21M18C-333B4LI-TR			IS61QDP2B21M18C1-333M3LI-TR
IS61QDP2B21M18C-333M3			IS61QDP2B21M18C1-400B4
IS61QDP2B21M18C-333M3-TR			IS61QDP2B21M18C2-333B4
IS61QDP2B21M18C-333M3I			IS61QDP2B21M18C2-333B4-TR
IS61QDP2B21M18C-333M3I-TR			IS61QDP2B21M18C2-333B4I
IS61QDP2B21M18C-333M3L			IS61QDP2B21M18C2-333B4I-TR
IS61QDP2B21M18C-333M3L-TR			IS61QDP2B21M18C2-333B4L
IS61QDP2B21M18C-333M3LI			IS61QDP2B21M18C2-333B4L-TR
IS61QDP2B21M18C-333M3LI-TR			IS61QDP2B21M18C2-333B4LI
IS61QDP2B21M18C-400B4			IS61QDP2B21M18C2-333B4LI-TR
IS61QDP2B21M18C-400B4-TR			IS61QDP2B21M18C2-333M3
IS61QDP2B21M18C1-333B4			IS61QDP2B21M18C2-333M3-TR
IS61QDP2B21M18C1-333B4-TR			IS61QDP2B21M18C2-333M3I
IS61QDP2B21M18C1-333B4I			IS61QDP2B21M18C2-333M3I-TR
IS61QDP2B21M18C1-333B4I-TR			IS61QDP2B21M18C2-333M3L
IS61QDP2B21M18C1-333B4L			IS61QDP2B21M18C2-333M3L-TR
IS61QDP2B21M18C1-333B4L-TR			IS61QDP2B21M18C2-333M3LI
IS61QDP2B21M18C1-333B4LI			IS61QDP2B21M18C2-333M3LI-TR
IS61QDP2B21M18C1-333B4LI-TR

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