1. 矽成
  2. 靜態隨機存取存儲器
  3. QUAD/QUADP and DDR-II/DDR-IIP
  4. DDR-IIP, Common I/O
  5. 72M 2Mx36
  6. IS61DDPB22M36B

  IS61DDPB22M36B

數據表
索取報價
容量 72M
規格 2Mx36
陣 2
狀態 Prod
速度Mhz 400, 450, 500, 550
評論上一版本 2.5 Cycle Read
數據表
索取報價

IS61DDPB22M36B 特徵

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes
  • Data-in for first burst addresses
  • Data-Out for second burst addresses The following are registered on the rising edge of the K# clock:
  • Boundary scan using limited set of JTAG 1149.1
  • Byte writes functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mm x 15mm & 15mm x 17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • Data Valid Pin (QVLD).
  • ODT (On Die Termination) feature is supported
  • optionally on data input, K/K#, and BWx#. The end of top mark (B/B1/B2) is to define options. IS61DDPB21M36B : Don’t care ODT function and pin connection IS61DDPB21M36B1 : Option1 IS61DDPB21M36B2 : Option 2 Refer to more detail description at page 6 for each ODT option.
  • Data-in for second burst addresses

概觀

The 36Mb IS61DDPB21M36B/B1/B2 and IS61DDPB22M18B/B1/B2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS61DDPB22M36B-TR IS61DDPB22M36B2
IS61DDPB22M36B1 IS61DDPB22M36B2-TR
IS61DDPB22M36B1-TR