1. 矽成
  2. 靜態隨機存取存儲器
  3. 同步 SRAM
  4. Automotive
  5. 2.5V
  6. QFP(100)
  7. IS64VF12832A-7-TR

  IS64VF12832A-7-TR

數據表
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規格 128Kx32
腳位/封裝 QFP(100)
tKQ 7.5
電壓 2.5V
VccQ 2.5V
狀態 Prod
評注 F
外包裝 Tape on reel
速度（MHz） 117
數據表
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IS64VF12832A-7-TR 特徵

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth expan- sion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • Power Supply LF: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VF: Vdd 2.5V -5% +10%, Vddq 2.5V -5% +10%
  • JEDEC 100-Pin QFP, 119-pin BGA, and 165-pin BGA packages
  • Automotive temperature available

概觀

The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64) LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 words by 32 bits. The IS61(64)LF/ VF12836A is organized as 131,072 words by 36 bits. The IS61(64)LF/VF25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technol- ogy, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.