規格 4Mx18
VccQ 1.8V
電壓 1.8V
tKQ 7.5
速度(MHz) 117
腳位/封裝 QFP(100), BGA(165), BGA(119)
狀態 Prod
型號別 IBIS
評注 F
相關IC编號
IS61VVF409618B-7-TR

IS61VVF409618B-7 特徵

  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth expan- sion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for PBGA package
  • Power Supply LF: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VF: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVF: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
  • JEDEC 100-Pin TQFP, 119-pin PBGA, and 165- pin PBGA packages

概觀

The 72Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and network- ing applications. The IS61LF/VF204836B is organized as 2,096,952 words by 36 bits. The IS61LF/VF409618B is organized as 4,193,904 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high- drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be writ- ten. Byte write operation is performed by using byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be gener- ated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Inter- leave burst is achieved when this pin is tied HIGH or left floating.