規格 256Kx72
VccQ 2.5V
電壓 2.5V
tKQ 2.6, 3.1
速度(MHz) 250, 200
腳位/封裝 BGA(209)
狀態 Prod
型號別 IBIS, BSDL
評注 P
外包裝 卷轴包

IS61NVP25672-250B1-TR 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball PBGA and 209-ball (x72) PBGA packages
  • Power supply: NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available
  • Lead-free available

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , Internal self-timed write cycle , Individual Byte Write Control , Single R/W (Read/Write) control pin , Clock controlled, registered address,