規格 2Mx18
VccQ 2.5/3.3V
電壓 3.3V
tKQ 2.6, 3.1, 3.5
速度(MHz) 200
腳位/封裝 B2 = BGA
狀態 Prod
評注 P, IS61NLP204818A
產品系列 61 = 高速
焊接 L = 無鉛
温規 I = 工業級 (-40C to +85°C)
相關IC编號
IS61NLP204818B-200B2LI-TR
IS61NLP204818B-166B2
IS61NLP204818B-166B2-TR
IS61NLP204818B-166B2I
IS61NLP204818B-166B2I-TR
IS61NLP204818B-166B2L
IS61NLP204818B-166B2L-TR
IS61NLP204818B-166B2LI
IS61NLP204818B-166B2LI-TR
IS61NLP204818B-166B3
IS61NLP204818B-166B3-TR
IS61NLP204818B-166B3I
IS61NLP204818B-166B3I-TR
IS61NLP204818B-166B3L
IS61NLP204818B-166B3L-TR
IS61NLP204818B-166B3LI
IS61NLP204818B-166B3LI-TR
IS61NLP204818B-166TQ
IS61NLP204818B-166TQ-TR
IS61NLP204818B-166TQI
IS61NLP204818B-166TQI-TR
IS61NLP204818B-166TQL
IS61NLP204818B-166TQL-TR
IS61NLP204818B-166TQLI
IS61NLP204818B-166TQLI-TR
IS61NLP204818B-200B2
IS61NLP204818B-200B2-TR
IS61NLP204818B-200B2I
IS61NLP204818B-200B2I-TR
IS61NLP204818B-200B2L
IS61NLP204818B-200B2L-TR
IS61NLP204818B-200B3
IS61NLP204818B-200B3-TR
IS61NLP204818B-200B3I
IS61NLP204818B-200B3I-TR
IS61NLP204818B-200B3L
IS61NLP204818B-200B3L-TR
IS61NLP204818B-200B3LI
IS61NLP204818B-200B3LI-TR
IS61NLP204818B-200TQ
IS61NLP204818B-200TQ-TR
IS61NLP204818B-200TQI
IS61NLP204818B-200TQI-TR
IS61NLP204818B-200TQL
IS61NLP204818B-200TQL-TR
IS61NLP204818B-200TQLI
IS61NLP204818B-200TQLI-TR
IS61NLP204818B-250B2
IS61NLP204818B-250B2-TR
IS61NLP204818B-250B2I
IS61NLP204818B-250B2I-TR
IS61NLP204818B-250B2L
IS61NLP204818B-250B2L-TR
IS61NLP204818B-250B2LI
IS61NLP204818B-250B2LI-TR
IS61NLP204818B-250B3
IS61NLP204818B-250B3-TR
IS61NLP204818B-250B3I
IS61NLP204818B-250B3I-TR
IS61NLP204818B-250B3L
IS61NLP204818B-250B3L-TR
IS61NLP204818B-250B3LI
IS61NLP204818B-250B3LI-TR
IS61NLP204818B-250TQ
IS61NLP204818B-250TQ-TR
IS61NLP204818B-250TQI
IS61NLP204818B-250TQI-TR
IS61NLP204818B-250TQL
IS61NLP204818B-250TQL-TR
IS61NLP204818B-250TQLI
IS61NLP204818B-250TQLI-TR


IS61NLP204818B-200B2LI 特徵

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, Internal self-timed write cycle Individual Byte Write Control
  • data and control Interleaved or linear burst sequence control us- ing MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
  • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NVVP: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
  • JTAG Boundary Scan for PBGA packages

概觀

, 100 percent bus utilization , No wait cycles between Read and Write , , , Single R/W (Read/Write) control pin , Clock controlled, registered address,