1. 矽成
2. 靜態隨機存取存儲器
3. 同步 SRAM
4. Pipeline
5. 3.3V
6. BGA
7. IS61LPS25636B-200B2I-TR

IS61LPS25636B-200B2I-TR 特徵

• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex- pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• JTAG Boundary Scan for BGA package
• Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
• JEDEC 100-Pin QFP, 119-ball BGA, and 165- ball BGA packages

概觀

The 9Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and net- working applications. The IS61LPS/VPS25636B and IS64LPS25636B are organized as 262,144 words by 36 bits. The IS61LPS25632B is organized as 262,144 words by 32 bits. The IS61LPS/VPS51218B is organized as 524,288 words by 18 bits. Fabricated with ISSI's ad- vanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.