規格 2Mx18
VccQ 2.5/3.3V
電壓 3.3V
tKQ 2.6, 3.1, 3.5
速度(MHz) 200
腳位/封裝 B2 = BGA
狀態 Prod
型號別 IBIS
評注 P/SCD, IS61LPS204818A
產品系列 61 = 高速
焊接 [空白] = SnPb
温規 I = 工業級 (-40C to +85°C)
外包裝 卷轴包
相關IC编號
IS61LPS204818B-200B2I
IS61LPS204818B-166B2
IS61LPS204818B-166B2-TR
IS61LPS204818B-166B2I
IS61LPS204818B-166B2I-TR
IS61LPS204818B-166B2L
IS61LPS204818B-166B2L-TR
IS61LPS204818B-166B2LI
IS61LPS204818B-166B2LI-TR
IS61LPS204818B-166B3
IS61LPS204818B-166B3-TR
IS61LPS204818B-166B3I
IS61LPS204818B-166B3I-TR
IS61LPS204818B-166B3L
IS61LPS204818B-166B3L-TR
IS61LPS204818B-166B3LI
IS61LPS204818B-166B3LI-TR
IS61LPS204818B-166TQ
IS61LPS204818B-166TQ-TR
IS61LPS204818B-166TQI
IS61LPS204818B-166TQI-TR
IS61LPS204818B-166TQL
IS61LPS204818B-166TQL-TR
IS61LPS204818B-166TQLI
IS61LPS204818B-166TQLI-TR
IS61LPS204818B-200B2
IS61LPS204818B-200B2-TR
IS61LPS204818B-200B2L
IS61LPS204818B-200B2L-TR
IS61LPS204818B-200B2LI
IS61LPS204818B-200B2LI-TR
IS61LPS204818B-200B3
IS61LPS204818B-200B3-TR
IS61LPS204818B-200B3I
IS61LPS204818B-200B3I-TR
IS61LPS204818B-200B3L
IS61LPS204818B-200B3L-TR
IS61LPS204818B-200B3LI
IS61LPS204818B-200B3LI-TR
IS61LPS204818B-200TQ
IS61LPS204818B-200TQ-TR
IS61LPS204818B-200TQI
IS61LPS204818B-200TQI-TR
IS61LPS204818B-200TQL
IS61LPS204818B-200TQL-TR
IS61LPS204818B-200TQLI
IS61LPS204818B-200TQLI-TR
IS61LPS204818B-250B2
IS61LPS204818B-250B2-TR
IS61LPS204818B-250B2I
IS61LPS204818B-250B2I-TR
IS61LPS204818B-250B2L
IS61LPS204818B-250B2L-TR
IS61LPS204818B-250B2LI
IS61LPS204818B-250B2LI-TR
IS61LPS204818B-250B3
IS61LPS204818B-250B3-TR
IS61LPS204818B-250B3I
IS61LPS204818B-250B3I-TR
IS61LPS204818B-250B3L
IS61LPS204818B-250B3L-TR
IS61LPS204818B-250B3LI
IS61LPS204818B-250B3LI-TR
IS61LPS204818B-250TQ
IS61LPS204818B-250TQ-TR
IS61LPS204818B-250TQI
IS61LPS204818B-250TQI-TR
IS61LPS204818B-250TQL
IS61LPS204818B-250TQL-TR
IS61LPS204818B-250TQLI
IS61LPS204818B-250TQLI-TR


IS61LPS204818B-200B2I-TR 特徵

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth ex- pansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for BGA package
  • Power Supply LPS: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%) VPS: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%) VVPS: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)
  • JEDEC 100-Pin QFP, 119-ball BGA, and 165- ball BGA packages

概觀

The 36Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and net- working applications. The IS61LPS/VPS102436B and IS64LPS102436B are organized as 1,048,476 words by 36 bits. The IS61LPS102432B is organized as 1,048,476 words by 32 bits. The IS61LPS/VPS204818B is organized as 2,096,952 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high- drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.