規格 256Kx36
VccQ 2.5/3.3V
電壓 3.3V
tKQ 2.6, 3.1
速度(MHz) 200
腳位/封裝 B3 = BGA
狀態 Prod
型號別 IBIS, BSDL
評注 P/DCD
產品系列 61 = 高速
焊接 [空白] = SnPb
温規 [空白] = 商規 (0C to +70°C)
外包裝 卷轴包

IS61LPD25636A-200B3-TR 特徵

  • Internal self-timed write cycle D51218A are high-speed, low-power synchronous static
  • Individual Byte Write Control and Global Write RAMs designed to provide burstable, high-performance memory for communication and networking applications.
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth ex- pansion and address pipelining control
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Double cycle deselect
  • Snooze MODE for reduced-power standby
  • JTAG Boundary Scan for PBGA package
  • Power Supply LPD: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPD: Vdd 2.5V + 5%, Vddq 2.5V + 5%
  • JEDEC 100-Pin TQFP, 119-pin PBGA and 165-pin PBGA package

概觀

The ISSI IS61LPD/VPD25636A and IS61LPD/VP- , Internal self-timed write cycle D51218A are high-speed, low-power synchronous static , Individual Byte Write Control and Global Write RAMs designed to provide burstable, high-performance memory for communication and networking applications. , Clock controlled, registered address, data and The IS61LPD/VPD25636A is organized as 262,144 words by 36 bits, and the IS61LPD/VPD51218A is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- edge-triggered single clock input.