IS45S32200L-7TLA2-TR

容量 64M
規格 2Mx32
電壓 3.3V
類型 SDR
刷新 4K
速度 7 = 143MHz
狀態 Prod
評注
腳位數 TSOP2(86), BGA(90)
温度等级 A2 = Automotive Grade (-40°C to +105°C)
焊料類型 L = 100% matte Sn
Generation L = L
字數 200 = 2M
工作電壓範圍 S = 3.3V SDR
總線寬度 32 = x32
腳位/封裝 T = TSOP
產品系列 45 = SDR Automotive grade
外包裝 Tape on Reel

IS45S32200L-7TLA2-TR 特徵

  • Clock frequency: 200, 166, 143, 133 MHz
  • Fully synchronous; all signals referenced to a positive clock edge
  • Internal bank for hiding row access/precharge
  • Single 3.3V power supply
  • LVTTL interface
  • Programmable burst length: (1, 2, 4, 8, full page)
  • Programmable burst sequence: Sequential/Interleave
  • Self refresh modes
  • 4096 refresh cycles every 16ms (A2 grade) or 64ms (Commercia, Industrial, A1 grade)
  • Random column address every clock cycle
  • Programmable CAS latency (2, 3 clocks)
  • Burst read/write and burst read/single write operations capability
  • Burst termination by burst stop and precharge command OPTIONS
  • Packages: 86-pin TSOP-II 90-ball TF-BGA

概觀

ISSI's 64Mb Synchronous DRAM IS42/45S32200L is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

 

相關IC编號

IC 編號 庫存數量 可用數量 IC 編號 庫存數量 可用數量
IS45S32200L-7TLA2 6,025 IS45S32200L-7BA1-TR
IS45S32200L IS45S32200L-7BLA1 6,951
IS45S32200L-6BLA1 6,997 IS45S32200L-7BLA1-TR 7,500
IS45S32200L-6BLA1-TR 7,500 IS45S32200L-7BLA2 60
IS45S32200L-6TLA1 6,440 IS45S32200L-7BLA2-TR 5,000
IS45S32200L-6TLA1-TR 6,500 IS45S32200L-7TLA1 10,800
IS45S32200L-7BA1 IS45S32200L-7TLA1-TR 6,500