IS49RL18320A-083FBLI-TR
特徵
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Clock cycle and
tRC timing
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- 0.83ns and tRC (MIN) = 6.67ns (RL3-2400) for -083F
- 0.83ns and tRC (MIN) = 7.5ns (RL3-2400) for -083E
- 0.93ns and tRC (MIN) = 7.5ns (RL3-2133) for -093F
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0.93ns and tRC (MIN) = 8.0ns (RL3-2133) for -093E
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1.07ns and tRC (MIN) = 8.0ns (RL3-1866) for -107E
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1200 MHz DDR operation (2400 Mb/s/ball
data rate)
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Organization
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32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
16 banks
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1.2V center-terminated push/pull I/O
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2.5V VEXT, 1.35V VDD, 1.2V VDDQ (optional 1.35V VDDQ
for 2400 operation only).
Reduced cycle time (tRC (MIN) = 6.67 - 8ns)
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SDR addressing
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Programmable READ/WRITE latency (RL/WL) and
burst length
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Data mask for WRITE commands
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Fr
DK x#) and output data clocks (QK x, QK x#)
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On-die DLL generates CK edge-aligned data and
x,
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64ms refresh (128K refresh per 64ms)
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40 Ω or 60 Ω matched impedance outputs
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Integrated on-die termination (ODT)
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Single or multibank writes
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Extended operating range (200
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READ training register
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Multiplexed and non-multiplexed addressing capa-
bilities
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Mirror function
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Output driver and ODT calibration
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Post Package Repar - 1 row per half bank