IS49NLS96400A-25WBLI-TR
特徵
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533MHz DDR operation (1.067 Gb/s/pin data rate)
38.4Gb/s peak bandwidth (x18 at 533 MHz clock
frequency)
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Reduced cycle time (15ns at 533MHz)
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32ms refresh (16K refresh for each bank; 128K
refresh command must be issued in total each
32ms)
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8 internal banks
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Non-multiplexed addresses (address
multiplexing option available)
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SRAM-type interface
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Programmable READ latency (RL), row cycle
time, and burst sequence length
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Balanced READ and WRITE latencies in order
to optimize data bus utilization
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Data mask signals (DM) to mask signal of
WRITE data; DM is sampled on both edges of
DK.
OPTIONS
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Package:
144-ball WBGA (lead-free)
NOVEMBER 2017
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Differential input clocks (CK, CK#)
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Differential input data clocks (DKx, DKx#)
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On-die DLL generates CK edge-aligned data
and output data clock signals
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Data valid signal (QVLD)
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HSTL I/O (1.5V or 1.8V nominal)
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25-60Ω matched impedance outputs
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2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
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On-die termination (ODT) RTT
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Operating temperature:
IEEE 1149.1 compliant JTAG boundary scan
Commercial
(TC = 0° to +95°C)
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
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Configuration:
64Mx9
32Mx18