規格 64Mx9
接口 Separate I/O
速度 25E = tCK = 2.5ns; tRC = 15ns
腳位/封裝 BGA(144)
狀態 Prod
產品系列 49NL = RLDRAM®2
焊接 L = 無鉛
温規 I = 工業級 (-40C to +85°C)

IS49NLS96400-25EBLI 特徵

  • Differential input clocks (CK, CK#)
  • Differential input data clocks (DKx, DKx#)
  • On-die DLL generates CK edge-aligned data and 400MHz DDR operation (800Mb/s/pin data rate) 14.4 Gb/s peak bandwidth (x18 Separate I/O at 400 MHz clock frequency) DECEMBER 2012
  • Reduced cycle time (15ns at 400MHz)
  • 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms) 8 internal banks
  • Non-multiplexed addresses (address multiplexing
  • option available) SRAM-type interface Programmable READ latency (RL), row cycle time, and burst sequence length
  • Balanced READ and WRITE latencies in order to optimize data bus utilization
  • Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. output data clock signals
  • Data valid signal (QVLD)
  • HSTL I/O (1.5V or 1.8V nominal)
  • On-die termination (ODT) RTT
  • Operating temperature: 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C) OPTIONS
  • Package: − 144-ball FBGA (leaded) − 144-ball FBGA (lead-free) Configuration: − 64Mx9 − 32Mx18 Clock Cycle Timing:


Supply voltage Ground DQ power supply DQ Ground Supply voltage Reference voltage Termination voltage Address - A0-22 Banks - BA0-2 Input data Output data Input data clock(Differential inputs) Output data clocks(outputs) Input clocks (CK, CK#) Input data mask.