| 容量 | 288M |
|---|---|
| 規格 | 8Mx36 |
| 狀態 | Prod |
| 評注 | |
| 接口 | Common I/O |
| 腳位數 | BGA(144) |
| 產品系列 | 49NL = RLDRAM 2 |
| 配置 | 36800 = 8M x 36 |
| 包裝代碼 | WB = WB |
| 速度等級 | 25E = tCK = 2.5ns; tRC = 15ns |
| ROHS版 | L = Lead-free (RoHS compliant) |
| Package Number | WB = 144 - ball WBGA (RLDRAM 2) |
| I / O類型 | C = Common I/O |
| 溫度範圍 | = Commercial (0C to 70°C) |
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.