IS49NLC18160-33BL - 日耀电子 | ISSI/蕊成授权代理

容量	288M
規格	32Mx9
腳位/封裝	BGA(144)
速度	tCK = 3.3ns; tRC = 20ns
焊接	Lead-free (RoHS Compliant)
狀態	Prod
接口	Common I/O
温規	Commercial Grade (0C to +70°C)
產品系列	49NL = RLDRAM 2
配置	18160 = 16M x 18
包裝代碼	B = B
速度等級	33 = tCK = 3.3ns; tRC = 20ns
ROHS版	L = Lead-free (RoHS compliant)
Package Number	B = 144-ball FBGA (RLDRAM 2)
I / O類型	C = Common I/O
溫度範圍	= Commercial (0C to 70°C)

數據表

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IS49NLC18160-33BL 特徵

400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency)
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
Reduced cycle time (15ns at 400MHz)
32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms) 8 internal banks
Non-multiplexed addresses (address multiplexing
option available) SRAM-type interface Programmable READ latency (RL), row cycle time, and burst sequence length
Balanced READ and WRITE latencies in order to optimize data bus utilization
Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. output data clock signals
Data valid signal (QVLD)
HSTL I/O (1.5V or 1.8V nominal)
On-die termination (ODT) RTT
Operating temperature: 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C) OPTIONS Package:

概觀

Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.