容量 | 288M |
---|---|
規格 | 16Mx18 |
狀態 | Prod |
評注 | |
接口 | Common I/O |
腳位數 | BGA(144) |
產品系列 | 49NL = RLDRAM 2 |
配置 | 18160 = 16M x 18 |
包裝代碼 | WB = WB |
速度等級 | 25E = tCK = 2.5ns; tRC = 15ns |
ROHS版 | L = Lead-free (RoHS compliant) |
Package Number | WB = 144 - ball WBGA (RLDRAM 2) |
I / O類型 | C = Common I/O |
溫度範圍 | = Commercial (0C to 70°C) |
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
IC 編號 | 庫存數量 | 可用數量 | IC 編號 | 庫存數量 | 可用數量 |
---|---|---|---|---|---|
IS49NLC18160-25EWBL-TR | IS49NLC18160-33WBL-TR | ||||
IS49NLC18160 | IS49NLC18160-33WBLI | 3 | |||
IS49NLC18160-25EWBLI | 100,000 | IS49NLC18160-33WBLI-TR | |||
IS49NLC18160-25EWBLI-TR | IS49NLC18160-5WBL | ||||
IS49NLC18160-25WBL | 100,000 | IS49NLC18160-5WBL-TR | |||
IS49NLC18160-25WBL-TR | IS49NLC18160-5WBLI | ||||
IS49NLC18160-25WBLI | 100,000 | IS49NLC18160-5WBLI-TR | |||
IS49NLC18160-25WBLI-TR | IS49NLC18160-TR | ||||
IS49NLC18160-33WBL | 100,000 |