| 容量 | 72M |
|---|---|
| 規格 | 4Mx18 |
| 陣 | 4 |
| 狀態 | Prod |
| 速度Mhz | 450, 500, 550, 567 |
| 評論上一版本 | 2.5 Cycle Read Latency, IS61QDPB24M18A/A1/A2 |
| 產品系列 | 61 = QUAD/P DDR-2/P |
| 配置 | 4M18 = 4M x18 |
| 包裝代碼 | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS版 | = Leaded |
| 突發類型 | B4 = Burst 4 |
| 硅片版本 | C = C |
| 讀延時（RL） | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT選項 | 1 = ODT Option 1 If ODT = HIGH or floating, a high range termination resistance is selected. If ODT = LOW, a low range termination resistance is selected. |
| 產品類別 | QDP = QUADP |
| 溫度範圍 | I = Industrial (-40°C to +85°C) |
| 速度 | 500 = 500MHz |
| 外包裝 | Tape on Reel |
The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: