規格 1Mx36
4
速度(MHz) 567
腳位/封裝 B4 = 165 ball BGA (13 x 15 mm)
狀態 Prod
型號別 ibis/verilog
評注 2.5 Cycle Read Latency
產品系列 61 = 高速
產品類別 QDP = QUADP
讀延時(RL) [空白] = 2.5 clock cycles
焊接 [空白] = 含鉛
温規 I = 工業級 (-40C to +85°C)
相關IC编號
IS61QDPB41M36C1-567B4I-TR
IS61QDPB41M36C-400B4
IS61QDPB41M36C-400B4-TR
IS61QDPB41M36C-400B4L
IS61QDPB41M36C-400B4L-TR
IS61QDPB41M36C-450B4
IS61QDPB41M36C-450B4-TR
IS61QDPB41M36C-450B4I
IS61QDPB41M36C-450B4I-TR
IS61QDPB41M36C-450B4L
IS61QDPB41M36C-450B4L-TR
IS61QDPB41M36C-450B4LI
IS61QDPB41M36C-450B4LI-TR
IS61QDPB41M36C-450M3
IS61QDPB41M36C-450M3-TR
IS61QDPB41M36C-450M3I
IS61QDPB41M36C-450M3I-TR
IS61QDPB41M36C-450M3L
IS61QDPB41M36C-450M3L-TR
IS61QDPB41M36C-450M3LI
IS61QDPB41M36C-450M3LI-TR
IS61QDPB41M36C-500B4
IS61QDPB41M36C-500B4-TR
IS61QDPB41M36C-500B4I
IS61QDPB41M36C-500B4I-TR
IS61QDPB41M36C-500B4L
IS61QDPB41M36C-500B4L-TR
IS61QDPB41M36C-500B4LI
IS61QDPB41M36C-500B4LI-TR
IS61QDPB41M36C-500M3
IS61QDPB41M36C-500M3-TR
IS61QDPB41M36C-500M3I
IS61QDPB41M36C-500M3I-TR
IS61QDPB41M36C-500M3L
IS61QDPB41M36C-500M3L-TR
IS61QDPB41M36C-500M3LI
IS61QDPB41M36C-500M3LI-TR
IS61QDPB41M36C-550B4I
IS61QDPB41M36C-550B4I-TR
IS61QDPB41M36C-550B4LI
IS61QDPB41M36C-550B4LI-TR
IS61QDPB41M36C-550M3
IS61QDPB41M36C-550M3-TR
IS61QDPB41M36C-550M3I
IS61QDPB41M36C-550M3I-TR
IS61QDPB41M36C-550M3L
IS61QDPB41M36C-550M3L-TR
IS61QDPB41M36C-550M3LI
IS61QDPB41M36C-550M3LI-TR
IS61QDPB41M36C-567B4
IS61QDPB41M36C-567B4-TR
IS61QDPB41M36C-567B4I
IS61QDPB41M36C-567B4I-TR
IS61QDPB41M36C-567B4L
IS61QDPB41M36C-567B4L-TR
IS61QDPB41M36C-567B4LI
IS61QDPB41M36C-567B4LI-TR
IS61QDPB41M36C-567M3
IS61QDPB41M36C-567M3-TR
IS61QDPB41M36C-567M3I
IS61QDPB41M36C-567M3I-TR
IS61QDPB41M36C-567M3L
IS61QDPB41M36C-567M3L-TR
IS61QDPB41M36C-567M3LI
IS61QDPB41M36C-567M3LI-TR
IS61QDPB41M36C1-400B4
IS61QDPB41M36C1-400B4-TR
IS61QDPB41M36C1-400B4L
IS61QDPB41M36C1-400B4L-TR
IS61QDPB41M36C1-450B4
IS61QDPB41M36C1-450B4-TR
IS61QDPB41M36C1-450B4I
IS61QDPB41M36C1-450B4I-TR
IS61QDPB41M36C1-450B4L
IS61QDPB41M36C1-450B4L-TR
IS61QDPB41M36C1-450B4LI
IS61QDPB41M36C1-450B4LI-TR
IS61QDPB41M36C1-450M3
IS61QDPB41M36C1-450M3-TR
IS61QDPB41M36C1-450M3I
IS61QDPB41M36C1-450M3I-TR
IS61QDPB41M36C1-450M3L
IS61QDPB41M36C1-450M3L-TR
IS61QDPB41M36C1-450M3LI
IS61QDPB41M36C1-450M3LI-TR
IS61QDPB41M36C1-500B4
IS61QDPB41M36C1-500B4-TR
IS61QDPB41M36C1-500B4I
IS61QDPB41M36C1-500B4I-TR
IS61QDPB41M36C1-500B4L
IS61QDPB41M36C1-500B4L-TR
IS61QDPB41M36C1-500B4LI
IS61QDPB41M36C1-500B4LI-TR
IS61QDPB41M36C1-500M3
IS61QDPB41M36C1-500M3-TR
IS61QDPB41M36C1-500M3I
IS61QDPB41M36C1-500M3I-TR
IS61QDPB41M36C1-500M3L
IS61QDPB41M36C1-500M3L-TR
IS61QDPB41M36C1-500M3LI
IS61QDPB41M36C1-500M3LI-TR
IS61QDPB41M36C1-550B4I
IS61QDPB41M36C1-550B4I-TR
IS61QDPB41M36C1-550B4LI
IS61QDPB41M36C1-550B4LI-TR
IS61QDPB41M36C1-550M3
IS61QDPB41M36C1-550M3-TR
IS61QDPB41M36C1-550M3I
IS61QDPB41M36C1-550M3I-TR
IS61QDPB41M36C1-550M3L
IS61QDPB41M36C1-550M3L-TR
IS61QDPB41M36C1-550M3LI
IS61QDPB41M36C1-550M3LI-TR
IS61QDPB41M36C1-567B4
IS61QDPB41M36C1-567B4-TR
IS61QDPB41M36C1-567B4L
IS61QDPB41M36C1-567B4L-TR
IS61QDPB41M36C1-567B4LI
IS61QDPB41M36C1-567B4LI-TR
IS61QDPB41M36C1-567M3
IS61QDPB41M36C1-567M3-TR
IS61QDPB41M36C1-567M3I
IS61QDPB41M36C1-567M3I-TR
IS61QDPB41M36C1-567M3L
IS61QDPB41M36C1-567M3L-TR
IS61QDPB41M36C1-567M3LI
IS61QDPB41M36C1-567M3LI-TR
IS61QDPB41M36C2-400B4
IS61QDPB41M36C2-400B4-TR
IS61QDPB41M36C2-400B4L
IS61QDPB41M36C2-400B4L-TR
IS61QDPB41M36C2-450B4
IS61QDPB41M36C2-450B4-TR
IS61QDPB41M36C2-450B4I
IS61QDPB41M36C2-450B4I-TR
IS61QDPB41M36C2-450B4L
IS61QDPB41M36C2-450B4L-TR
IS61QDPB41M36C2-450B4LI
IS61QDPB41M36C2-450B4LI-TR
IS61QDPB41M36C2-450M3
IS61QDPB41M36C2-450M3-TR
IS61QDPB41M36C2-450M3I
IS61QDPB41M36C2-450M3I-TR
IS61QDPB41M36C2-450M3L
IS61QDPB41M36C2-450M3L-TR
IS61QDPB41M36C2-450M3LI
IS61QDPB41M36C2-450M3LI-TR
IS61QDPB41M36C2-500B4
IS61QDPB41M36C2-500B4-TR
IS61QDPB41M36C2-500B4I
IS61QDPB41M36C2-500B4I-TR
IS61QDPB41M36C2-500B4L
IS61QDPB41M36C2-500B4L-TR
IS61QDPB41M36C2-500B4LI
IS61QDPB41M36C2-500B4LI-TR
IS61QDPB41M36C2-500M3
IS61QDPB41M36C2-500M3-TR
IS61QDPB41M36C2-500M3I
IS61QDPB41M36C2-500M3I-TR
IS61QDPB41M36C2-500M3L
IS61QDPB41M36C2-500M3L-TR
IS61QDPB41M36C2-500M3LI
IS61QDPB41M36C2-500M3LI-TR
IS61QDPB41M36C2-550B4I
IS61QDPB41M36C2-550B4I-TR
IS61QDPB41M36C2-550B4LI
IS61QDPB41M36C2-550B4LI-TR
IS61QDPB41M36C2-550M3
IS61QDPB41M36C2-550M3-TR
IS61QDPB41M36C2-550M3I
IS61QDPB41M36C2-550M3I-TR
IS61QDPB41M36C2-550M3L
IS61QDPB41M36C2-550M3L-TR
IS61QDPB41M36C2-550M3LI
IS61QDPB41M36C2-550M3LI-TR
IS61QDPB41M36C2-567B4
IS61QDPB41M36C2-567B4-TR
IS61QDPB41M36C2-567B4I
IS61QDPB41M36C2-567B4I-TR
IS61QDPB41M36C2-567B4L
IS61QDPB41M36C2-567B4L-TR
IS61QDPB41M36C2-567B4LI
IS61QDPB41M36C2-567B4LI-TR
IS61QDPB41M36C2-567M3
IS61QDPB41M36C2-567M3-TR
IS61QDPB41M36C2-567M3I
IS61QDPB41M36C2-567M3I-TR
IS61QDPB41M36C2-567M3L
IS61QDPB41M36C2-567M3L-TR
IS61QDPB41M36C2-567M3LI
IS61QDPB41M36C2-567M3LI-TR


IS61QDPB41M36C1-567B4I 特徵

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data Valid Pin (QVLD).
  • HSTL input and output levels.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user- supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes for burst addresses 1 and 3
  • Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K# clock:
  • Byte writes for burst addresses 2 and 4

概觀

The 36Mb IS61QDPB41M36C/C1/C2 and IS61QDPB42M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: