容量 | 72M |
---|---|
規格 | 4Mx18 |
陣 | 2 |
狀態 | Prod |
速度Mhz | 300, 333, 400, 450 |
評論上一版本 | 2.5 Cycle Read Latency |
產品系列 | 61 = QUAD/P DDR-2/P |
配置 | 4M18 = 4M x18 |
包裝代碼 | M3 = 165-ball BGA (15 x 17 mm) |
ROHS版 | L = Lead-free |
突發類型 | B2 = Burst 2 |
硅片版本 | C = C |
讀延時(RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
ODT選項 | 1 = ODT Option 1 If ODT = HIGH or floating, a high range termination resistance is selected. If ODT = LOW, a low range termination resistance is selected. |
產品類別 | QDP = QUADP |
溫度範圍 | blank = Commercial (0°C to 70°C) |
速度 | 450 = 450MHz |
外包裝 | Tape on Reel |
The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the description of the basic operations of these.