|腳位/封裝||M3 = 165-ball BGA (15 x 17 mm)|
|評注||2.5 Cycle Read Latency|
|產品系列||61 = 高速|
|產品類別||QDP = QUADP|
|讀延時（RL）||[空白] = 2.5 clock cycles|
|焊接||[空白] = 含鉛|
|温規||[空白] = 商規 (0C to +70°C)|
- 512Kx36 and 1Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with EARLY write operation.
- Double Data Rate (DDR) interface for read and write input ports. 2.5 Cycle read latency. Fixed 2-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
- Data valid pin (QVLD).
- HSTL input and output interface.
- Registered addresses, write and read controls, byte writes, data in, and data outputs.
- Full data coherency.
- Boundary scan using limited set of JTAG 1149.1 functions.
- Byte Write capability.
- Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
- Programmable impedance output drivers via 5x user- supplied precision resistor.
- ODT (On Die Termination) feature is supported
- Read address
- Read enable
- Write enable
- Data-in for early writes The following are registered on the rising edge of the K# clock:
- Write address
- Byte writes
The are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the for a description of the basic.