|腳位/封裝||B4 = 165 ball BGA (13 x 15 mm)|
|評注||2.0 Cycle Read Latency|
|產品系列||61 = 高速|
|產品類別||QDP = QUADP|
|讀延時（RL）||2 = 2 clock cycles|
|ODT選項||A2 = 選項2|
|焊接||[空白] = 含鉛|
|温規||[空白] = 商規 (0C to +70°C)|
- 1Mx36 and 2Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with late write operation.
- Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
- Data Valid Pin (QVLD).
- HSTL input and output interface. functions.
- Byte write capability.
- Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
- Programmable impedance output drivers via 5x user-supplied precision resistor.
- ODT (On Die Termination) feature is supported
- Read/write address
- Read enable
- Write enable
- Byte writes for burst addresses 1 and 3
- Data-in for burst addresses 1 and 3 Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first and third bursts are updated from output registers of the third and fourth rising edges of the K clock (starting 2.0 cycles later after read command). The data-outs from the second and fourth bursts are updated with the third and fourth rising edges of the K# clock where the read command receives at the first rising edge of K. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.
- Registered addresses, write and read controls, byte writes, data in, and data outputs. The following are registered on the rising edge of the K# clock:
- Full data coherency.
- Boundary scan using limited set of JTAG 1149.1
- Byte writes for burst addresses 2 and 4
The 36Mb IS61QDP2B41M36A/A1/A2 and IS61QDP2B42M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: