規格 2Mx18
2
速度(MHz) 400
腳位/封裝 M3 = 165-ball BGA (15 x 17 mm)
狀態 Prod
型號別 ibis/verilog
評注 2.0 Cycle Read Latency
產品系列 61 = 高速
產品類別 QDP = QUADP
讀延時(RL) 2 = 2 clock cycles
焊接 [空白] = 含鉛
温規 I = 工業級 (-40C to +85°C)
相關IC编號
IS61QDP2B22M18C-400M3I-TR
IS61QDP2B22M18C-333B4
IS61QDP2B22M18C-333B4-TR
IS61QDP2B22M18C-333B4I
IS61QDP2B22M18C-333B4I-TR
IS61QDP2B22M18C-333B4L
IS61QDP2B22M18C-333B4L-TR
IS61QDP2B22M18C-333B4LI
IS61QDP2B22M18C-333B4LI-TR
IS61QDP2B22M18C-333M3
IS61QDP2B22M18C-333M3-TR
IS61QDP2B22M18C-333M3I
IS61QDP2B22M18C-333M3I-TR
IS61QDP2B22M18C-333M3L
IS61QDP2B22M18C-333M3L-TR
IS61QDP2B22M18C-333M3LI
IS61QDP2B22M18C-333M3LI-TR
IS61QDP2B22M18C-400B4
IS61QDP2B22M18C-400B4-TR
IS61QDP2B22M18C-400B4I
IS61QDP2B22M18C-400B4I-TR
IS61QDP2B22M18C-400B4L
IS61QDP2B22M18C-400B4L-TR
IS61QDP2B22M18C-400B4LI
IS61QDP2B22M18C-400B4LI-TR
IS61QDP2B22M18C-400M3
IS61QDP2B22M18C-400M3-TR
IS61QDP2B22M18C-400M3L
IS61QDP2B22M18C-400M3L-TR
IS61QDP2B22M18C-400M3LI
IS61QDP2B22M18C-400M3LI-TR
IS61QDP2B22M18C-450B4
IS61QDP2B22M18C-450B4-TR
IS61QDP2B22M18C-450B4I
IS61QDP2B22M18C-450B4I-TR
IS61QDP2B22M18C-450B4L
IS61QDP2B22M18C-450B4L-TR
IS61QDP2B22M18C-450B4LI
IS61QDP2B22M18C-450B4LI-TR
IS61QDP2B22M18C-450M3
IS61QDP2B22M18C-450M3-TR
IS61QDP2B22M18C-450M3I
IS61QDP2B22M18C-450M3I-TR
IS61QDP2B22M18C-450M3L
IS61QDP2B22M18C-450M3L-TR
IS61QDP2B22M18C-450M3LI
IS61QDP2B22M18C-450M3LI-TR
IS61QDP2B22M18C1-333B4
IS61QDP2B22M18C1-333B4-TR
IS61QDP2B22M18C1-333B4I
IS61QDP2B22M18C1-333B4I-TR
IS61QDP2B22M18C1-333B4L
IS61QDP2B22M18C1-333B4L-TR
IS61QDP2B22M18C1-333B4LI
IS61QDP2B22M18C1-333B4LI-TR
IS61QDP2B22M18C1-333M3
IS61QDP2B22M18C1-333M3-TR
IS61QDP2B22M18C1-333M3I
IS61QDP2B22M18C1-333M3I-TR
IS61QDP2B22M18C1-333M3L
IS61QDP2B22M18C1-333M3L-TR
IS61QDP2B22M18C1-333M3LI
IS61QDP2B22M18C1-333M3LI-TR
IS61QDP2B22M18C1-400B4
IS61QDP2B22M18C1-400B4-TR
IS61QDP2B22M18C1-400B4I
IS61QDP2B22M18C1-400B4I-TR
IS61QDP2B22M18C1-400B4L
IS61QDP2B22M18C1-400B4L-TR
IS61QDP2B22M18C1-400B4LI
IS61QDP2B22M18C1-400B4LI-TR
IS61QDP2B22M18C1-400M3
IS61QDP2B22M18C1-400M3-TR
IS61QDP2B22M18C1-400M3I
IS61QDP2B22M18C1-400M3I-TR
IS61QDP2B22M18C1-400M3L
IS61QDP2B22M18C1-400M3L-TR
IS61QDP2B22M18C1-400M3LI
IS61QDP2B22M18C1-400M3LI-TR
IS61QDP2B22M18C1-450B4
IS61QDP2B22M18C1-450B4-TR
IS61QDP2B22M18C1-450B4I
IS61QDP2B22M18C1-450B4I-TR
IS61QDP2B22M18C1-450B4L
IS61QDP2B22M18C1-450B4L-TR
IS61QDP2B22M18C1-450B4LI
IS61QDP2B22M18C1-450B4LI-TR
IS61QDP2B22M18C1-450M3
IS61QDP2B22M18C1-450M3-TR
IS61QDP2B22M18C1-450M3I
IS61QDP2B22M18C1-450M3I-TR
IS61QDP2B22M18C1-450M3L
IS61QDP2B22M18C1-450M3L-TR
IS61QDP2B22M18C1-450M3LI
IS61QDP2B22M18C1-450M3LI-TR
IS61QDP2B22M18C2-333B4
IS61QDP2B22M18C2-333B4-TR
IS61QDP2B22M18C2-333B4I
IS61QDP2B22M18C2-333B4I-TR
IS61QDP2B22M18C2-333B4L
IS61QDP2B22M18C2-333B4L-TR
IS61QDP2B22M18C2-333B4LI
IS61QDP2B22M18C2-333B4LI-TR
IS61QDP2B22M18C2-333M3
IS61QDP2B22M18C2-333M3-TR
IS61QDP2B22M18C2-333M3I
IS61QDP2B22M18C2-333M3I-TR
IS61QDP2B22M18C2-333M3L
IS61QDP2B22M18C2-333M3L-TR
IS61QDP2B22M18C2-333M3LI
IS61QDP2B22M18C2-333M3LI-TR
IS61QDP2B22M18C2-400B4
IS61QDP2B22M18C2-400B4-TR
IS61QDP2B22M18C2-400B4I
IS61QDP2B22M18C2-400B4I-TR
IS61QDP2B22M18C2-400B4L
IS61QDP2B22M18C2-400B4L-TR
IS61QDP2B22M18C2-400B4LI
IS61QDP2B22M18C2-400B4LI-TR
IS61QDP2B22M18C2-400M3
IS61QDP2B22M18C2-400M3-TR
IS61QDP2B22M18C2-400M3I
IS61QDP2B22M18C2-400M3I-TR
IS61QDP2B22M18C2-400M3L
IS61QDP2B22M18C2-400M3L-TR
IS61QDP2B22M18C2-400M3LI
IS61QDP2B22M18C2-400M3LI-TR
IS61QDP2B22M18C2-450B4
IS61QDP2B22M18C2-450B4-TR
IS61QDP2B22M18C2-450B4I
IS61QDP2B22M18C2-450B4I-TR
IS61QDP2B22M18C2-450B4L
IS61QDP2B22M18C2-450B4L-TR
IS61QDP2B22M18C2-450B4LI
IS61QDP2B22M18C2-450B4LI-TR
IS61QDP2B22M18C2-450M3
IS61QDP2B22M18C2-450M3-TR
IS61QDP2B22M18C2-450M3I
IS61QDP2B22M18C2-450M3I-TR
IS61QDP2B22M18C2-450M3L
IS61QDP2B22M18C2-450M3L-TR
IS61QDP2B22M18C2-450M3LI
IS61QDP2B22M18C2-450M3LI-TR


IS61QDP2B22M18C-400M3I 特徵

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.0 Cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data valid pin (QVLD).
  • Read address
  • Read enable
  • Write enable
  • Data-in for early writes The following are registered on the rising edge of the K# clock:
  • Write address
  • Byte writes
  • Registered addresses, write and read controls, byte
  • Data-in for second burst addresses writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte Write capability.
  • Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user- supplied precision resistor.
  • ODT (On Die Termination) feature is supported

概觀

The are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the for a description of the basic.