規格 512Kx36
4
速度(MHz) 333
腳位/封裝 B4 = 165 ball BGA (13 x 15 mm)
狀態 Prod
型號別 ibis/verilog
產品系列 61 = 高速
產品類別 QD = QUAD
讀延時(RL) [空白] = 2.5 clock cycles
ODT選項 A = 無ODT
焊接 [空白] = 含鉛
温規 I = 工業級 (-40C to +85°C)
相關IC编號
IS61QDB451236A-333B4I-TR
IS61QDB451236A-250B4
IS61QDB451236A-250B4-TR
IS61QDB451236A-250B4I
IS61QDB451236A-250B4I-TR
IS61QDB451236A-250B4L
IS61QDB451236A-250B4L-TR
IS61QDB451236A-250B4LI
IS61QDB451236A-250B4LI-TR
IS61QDB451236A-250M3
IS61QDB451236A-250M3-TR
IS61QDB451236A-250M3I
IS61QDB451236A-250M3I-TR
IS61QDB451236A-250M3L
IS61QDB451236A-250M3L-TR
IS61QDB451236A-250M3LI
IS61QDB451236A-250M3LI-TR
IS61QDB451236A-300B4
IS61QDB451236A-300B4-TR
IS61QDB451236A-300B4I
IS61QDB451236A-300B4I-TR
IS61QDB451236A-300B4L
IS61QDB451236A-300B4L-TR
IS61QDB451236A-300B4LI
IS61QDB451236A-300B4LI-TR
IS61QDB451236A-300M3
IS61QDB451236A-300M3-TR
IS61QDB451236A-300M3I
IS61QDB451236A-300M3I-TR
IS61QDB451236A-300M3L
IS61QDB451236A-300M3L-TR
IS61QDB451236A-300M3LI
IS61QDB451236A-300M3LI-TR
IS61QDB451236A-333B4
IS61QDB451236A-333B4-TR
IS61QDB451236A-333B4L
IS61QDB451236A-333B4L-TR
IS61QDB451236A-333B4LI
IS61QDB451236A-333B4LI-TR
IS61QDB451236A-333M3
IS61QDB451236A-333M3-TR
IS61QDB451236A-333M3I
IS61QDB451236A-333M3I-TR
IS61QDB451236A-333M3L
IS61QDB451236A-333M3L-TR
IS61QDB451236A-333M3LI
IS61QDB451236A-333M3LI-TR
IS61QDB451236A-400B4
IS61QDB451236A-400B4-TR
IS61QDB451236A-400B4I
IS61QDB451236A-400B4I-TR
IS61QDB451236A-400B4L
IS61QDB451236A-400B4L-TR
IS61QDB451236A-400B4LI
IS61QDB451236A-400B4LI-TR
IS61QDB451236A-400M3
IS61QDB451236A-400M3-TR
IS61QDB451236A-400M3I
IS61QDB451236A-400M3I-TR
IS61QDB451236A-400M3L
IS61QDB451236A-400M3L-TR
IS61QDB451236A-400M3LI
IS61QDB451236A-400M3LI-TR


IS61QDB451236A-333B4I 特徵

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes for burst addresses 1 and 3
  • Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K# clock:
  • Registered addresses, write and read controls, byte
  • Byte writes for burst addresses 2 and 4 writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.

概觀

The 18Mb IS61QDB451236A and IS61QDB41M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: