規格 2Mx36
速度(MHz) 333
腳位/封裝 M3 = 165-ball BGA (15 x 17 mm)
狀態 Prod
型號別 ibis/verilog
評注 IS61QDB42M36A
產品系列 61 = 高速
產品類別 QD = QUAD
讀延時(RL) [空白] = 2.5 clock cycles
焊接 [空白] = 含鉛
温規 [空白] = 商規 (0C to +70°C)
外包裝 卷轴包

IS61QDB42M36C-333M3-TR 特徵

  • 2Mx36 and 4Mx18 configuration available.
  • Separate independent read and write ports with concurrent read and write operations.
  • Max. 400 MHz clock for high bandwidth
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Full data coherency.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array


The 72Mb IS61QDB42M36C and IS61QDB44M18C are syn- chronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initi- ates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. Byte writes can change with the corresponding data-in to en- able or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first and third bursts are updated from output registers of the sec- ond and third rising edges of the C# clock (starting 1.5 cycles later after read command). The data-outs from the second and fourth bursts are updated with the third and fourth rising edges of the C clock. The K and K# clocks are used to time the data-outs whenever the C and C# clocks are tied high. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.