|腳位/封裝||M3 = 165-ball BGA (15 x 17 mm)|
|評注||IS61QDB42M36, Application Note|
|產品系列||61 = 高速|
|產品類別||QD = QUAD|
|讀延時（RL）||[空白] = 2.5 clock cycles|
|ODT選項||A = 無ODT|
|焊接||[空白] = 含鉛|
|温規||I = 工業級 (-40C to +85°C)|
- 2Mx36 and 4Mx18 configuration available.
- On-chip Delay-Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with late write operation.
- Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Read/write address
- Read enable
- Write enable
- Byte writes for burst addresses 1 and 3
- Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K# clock:
- Registered addresses, write and read controls, byte
- Byte writes for burst addresses 2 and 4 writes, data in, and data outputs.
- Full data coherency.
- Boundary scan using limited set of JTAG 1149.1 functions.
- Byte write capability.
- Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
- Programmable impedance output drivers via 5x user-supplied precision resistor.
The 72Mb IS61QDB42M36A and IS61QDB44M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: