| 容量 | 18M |
|---|---|
| 規格 | 512Kx36 |
| 陣 | 4 |
| 狀態 | Prod |
| 速度Mhz | 300, 333, 400, 450 |
| 評論上一版本 | 2.5 Cycle Read |
| 產品系列 | 61 = QUAD/P DDR-2/P |
| 配置 | 51236 = 512K x36 |
| 包裝代碼 | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS版 | = Leaded |
| 突發類型 | B4 = Burst 4 |
| 硅片版本 | A = A |
| 讀延時（RL） | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT選項 | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
| 產品類別 | DDP = DDR-IIP, Common I/O |
| 溫度範圍 | I = Industrial (-40°C to +85°C) |
| 速度 | 450 = 450MHz |
| 外包裝 | Tape on Reel |
The 18Mb IS61DDPB451236A/A1/A2 and IS61DDPB41M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 4) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: