IS61DDPB24M18C-500B4LI

IS61DDPB24M18C-500B4LI 特徵

概觀

The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal opera- tions are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the third rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second burst are updated with the fourth rising edge of the K clock where read command receives at the first rising edge of K. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.