| 容量 | 36M |
|---|---|
| 規格 | 1Mx36 |
| 陣 | 2 |
| 狀態 | Prod |
| 速度Mhz | 300, 333, 400, 450 |
| 評論上一版本 | 2.0 Cycle Read |
| 產品系列 | 61 = QUAD/P DDR-2/P |
| 配置 | 1M36 = 1M x36 |
| 包裝代碼 | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS版 | L = Lead-free |
| 突發類型 | B2 = Burst 2 |
| 硅片版本 | C = C |
| 讀延時（RL） | 2 = 2.0 clock cycles |
| ODT選項 | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
| 產品類別 | DDP = DDR-IIP, Common I/O |
| 溫度範圍 | blank = Commercial (0°C to 70°C) |
| 速度 | 400 = 400MHz |
| 外包裝 | Tape on Reel |
The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self- timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: