1. 矽成
  2. 靜態隨機存取存儲器
  3. QUAD/QUADP and DDR-II/DDR-IIP
  4. DDR-IIP, Common I/O
  5. 18M 1Mx18
  6. 165 ball BGA (13 x 15 mm)
  7. IS61DDP2B21M18C-450B4L-TR

  IS61DDP2B21M18C-450B4L-TR

數據表
索取報價
容量 18M
規格 1Mx18
陣 2
狀態 Prod
速度Mhz 300, 333, 400, 450
評論上一版本 2.0 Cycle Read
產品系列 61 = QUAD/P DDR-2/P
配置 1M18 = 1M x18
包裝代碼 B4 = 165 ball BGA (13 x 15 mm)
ROHS版 L = Lead-free
突發類型 B2 = Burst 2
硅片版本 C = C
讀延時（RL） 2 = 2.0 clock cycles
ODT選項 blank = No ODT
產品類別 DDP = DDR-IIP, Common I/O
溫度範圍 blank = Commercial (0°C to 70°C)
速度 450 = 450MHz
外包裝 Tape on Reel
數據表
索取報價

IS61DDP2B21M18C-450B4L-TR 特徵

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user- supplied precision resistor.
  • Data Valid Pin (QVLD).
  • ODT (On Die Termination) feature is supported
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes
  • Data-in for first burst address
  • Data-Out for first burst address The following are registered on the rising edge of the K# clock:
  • Byte writes
  • Data-in for second burst address

概觀

The 18Mb IS61DDP2B251236C/C1/C2 and IS61DDP2B21M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self- timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edge of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

 

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IS61DDP2B21M18C1-333B4I IS61DDP2B21M18C2-333M3I-TR
IS61DDP2B21M18C1-333B4I-TR IS61DDP2B21M18C2-333M3L
IS61DDP2B21M18C1-333B4L IS61DDP2B21M18C2-333M3L-TR
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IS61DDP2B21M18C1-333B4LI-TR
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