1. 矽成
  2. 靜態隨機存取存儲器
  3. QUAD/QUADP and DDR-II/DDR-IIP
  4. DDR-II, Common I/O, Separate I/O
  5. 18M 512Kx36
  6. 165 ball BGA (13 x 15 mm)
  7. IS61DDB251236C-250B4

  IS61DDB251236C-250B4

數據表
索取報價
容量 18M
規格 512Kx36
陣 2
狀態 Prod
速度Mhz 250, 300, 333, 400
評論上一版本
產品系列 61 = QUAD/P DDR-2/P
配置 51236 = 512K x36
包裝代碼 B4 = 165 ball BGA (13 x 15 mm)
ROHS版 = Leaded
突發類型 B2 = Burst 2
硅片版本 C = C
讀延時（RL） blank = 1.5 clock cycles or 2.5 clock cycles
ODT選項 blank = No ODT
產品類別 DD = DDR-II, Common I/O
溫度範圍 blank = Commercial (0°C to 70°C)
速度 250 = 250MHz
數據表
索取報價

IS61DDB251236C-250B4 特徵

  • Read/write address
  • Read enable
  • Write enable
  • Byte writes for first burst address
  • Data-in for first burst address The following are registered on the rising edge of the K# clock.
  • Byte writes for second burst address
  • Data-in for second burst address Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the C# clock (starting one and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the C clock. The K and K# clocks are used to time the data-outs whenever the C and C# clocks are tied high. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. IS61DDB21M18C IS61DDB251236C
  • 512Kx36 and 1Mx18 configuration available.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two input clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array

概觀

The 18Mb IS61DDB251236C and IS61DDB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs.

 

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IS61DDB251236C-250M3L-TR IS61DDB251236C-333B4LI
IS61DDB251236C-250M3LI 10,000 IS61DDB251236C-333B4LI-TR
IS61DDB251236C-250M3LI-TR IS61DDB251236C-333M3
IS61DDB251236C-300B4 IS61DDB251236C-333M3-TR
IS61DDB251236C-300B4-TR IS61DDB251236C-333M3I
IS61DDB251236C-300B4I IS61DDB251236C-333M3I-TR
IS61DDB251236C-300B4I-TR IS61DDB251236C-333M3L 10,000
IS61DDB251236C-300B4L IS61DDB251236C-333M3L-TR
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IS61DDB251236C-300B4LI-TR IS61DDB251236C-400B4
IS61DDB251236C-300M3 IS61DDB251236C-400B4-TR
IS61DDB251236C-300M3-TR IS61DDB251236C-400B4I
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