IS61DDB24M18C-333B4L

容量	72M
規格	4Mx18
陣	2
狀態	Prod
速度Mhz	250, 300, 333, 400
評論上一版本	IS61DDB24M18A
產品系列	61 = QUAD/P DDR-2/P
配置	4M18 = 4M x18
包裝代碼	B4 = 165 ball BGA (13 x 15 mm)
ROHS版	L = Lead-free
突發類型	B2 = Burst 2
硅片版本	C = C
讀延時（RL）	blank = 1.5 clock cycles or 2.5 clock cycles
ODT選項	blank = No ODT
產品類別	DD = DDR-II, Common I/O
溫度範圍	blank = Commercial (0°C to 70°C)
速度	333 = 333MHz

IS61DDB24M18C-333B4L 特徵

2Mx36 and 4Mx18 configuration available.
Common I/O read and write ports.
Max. 400 MHz clock for high bandwidth
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two input clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.
HSTL input and output interface.
On-chip delay-locked loop (DLL) for wide data valid window.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array

The 72Mb IS61DDB22M36C and IS61DDB24M18C are syn- chronous, high-performance CMOS static random access memory (SRAM) devices.